To build an integrated circuit chip, a layer of selected materials is deposited on a silicon substrate using a variety of deposition techniques, including chemical vapor deposition, sputtering, ashing, and other techniques. Chemical mechanical planarization (CMP) usually is performed after depositing the layer. CMP provides smooth, planar topographies to semiconductor wafers and surfaces deposited on a semiconductor substrate, such as silicon, and is an integral part of making many types of integrated chips. The deposition and polishing steps are repeated as necessary to build a multi-layer integrated chip. For example, a layer of electrically conducting material is sputtered onto an etched substrate. The CMP process then is used to remove the layer until the electrically conducting material remains only in the etched areas. Subsequently, additional layers are added and then polished until the final product is achieved: many layers of integrated circuits on the built-up front side of the silicon substrate.
When building integrated chips it is important that the semiconductor substrate be very thin, as thin as 100 micrometers or even 75 micrometers (μm). To make the substrate as thin as possible, and to relieve stress caused during the deposition and CMP processes, the back of the wafer is ground to remove the bulk of the substrate. This process is known as backgrinding. However, stresses build up during the backgrinding process that tend to warp the wafer and make it vulnerable to breaking when the wafer is later cut into individual die. The stress is caused by small deformations on the surface of the substrate, typically grind lines, that arise from the physical force of grinding. In addition, the stress caused by backgrinding is exacerbated by internal stresses accumulated during the layer building process. Thus, it is important to relieve as much wafer stress as possible.
Currently, wafers are wet-etched with acid etchants to relieve stress after backgrinding. However, wet etching with acid poses four significant problems. First, the acid may damage the outer edge of the top layers of the wafer if the acid seeps through the protective means, such as backgrind tape, used protect the front side of the wafer. The damage can destroy integrated chips located around the edge of the wafer, thus reducing production efficiency. Second, using acids is inefficient. Wet etching with acids requires that the background wafers be transferred to a separate machine built to withstand the acids. The time required to transfer the wafers and conduct an additional process reduces the efficiency of chip production. In addition, a machine that can perform wet etching with acid is very expensive, both initially and operationally, thus making the process more expensive and less efficient. Third, transferring fragile wafers to a separate machine while the wafers are at a maximum state of stress increases the probability of damaging the wafers, thereby further reducing efficiency and increasing the cost of production. Fourth, the acids typically used in the etching process are environmentally toxic and difficult to dispose of properly. The cost of the acids, plus the cost of disposing of the acids, make the cost of using an acid wet etch process even more expensive. Thus, a new method for reducing wafer stress has been developed in order to avoid unnecessary damage to the integrated chips on the front side of the wafer, increase efficiency, reduce cost, and reduce environmental pollution.